As the semiconductor industry introduces new generations of integrated circuits (IC's) having higher performance and greater functionality, the density of the elements that form those IC's is increased, while the dimensions, sizes, and spacing between the individual components or elements are reduced. These device geometries having smaller dimensions are creating new manufacturing challenges. In a typical integrated circuit, there may be many metallization layers and interconnecting via layers formed in a back end of line (BEOL) interconnect structure. The BEOL interconnect structure connects various devices (e.g., transistors, capacitors, etc.) to form functional circuits. During fabrication, it is necessary to form cuts and connections amongst metal lines to create the needed connectivity. As critical dimensions continue to shrink, this can be challenging. It is therefore desirable to have improvements to address the aforementioned challenges.